EP1810GM883B vs EP1810JI-45 Comparación
Comparación detallada lado a lado de EP1810GM883B por Altera y EP1810JI-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810GM883B | EP1810JI-45 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $125,40 | $9,75 |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | — |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | 50 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Temperatura de funcionamiento | -55 °C to +125 °C (Military, MIL-STD-883B) | -40 °C to +85 °C |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | UV-erase (windowed) / OTP via JEDEC |
| Tipo de montaje | Through-hole (PGA socket or PCB through-hole) | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Configurable I/O Lines | — | 48 |
| Package Code | — | QCCJ |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| Tensión de alimentación | — | 5 V (TTL compatible) |