EP1810JC-35 vs EP1810JC-25 Comparación
Comparación detallada lado a lado de EP1810JC-35 por Intel y EP1810JC-25 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-35 | EP1810JC-25 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,48 | $6,80 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| Frecuencia de reloj máxima | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Rango de temperatura de funcionamiento | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | UV light (windowed package) |
| Estado RoHS | Compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Tipo de montaje | Surface Mount (J-Lead) | Through-hole |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera/Intel Classic EPLD (EP1810 series) |
| Macrocells | — | 48 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Temperatura de funcionamiento | — | -40 °C to 85 °C (industrial, per distributor listings) |
| Technology | — | CMOS, UV-erasable (windowed ceramic DIP) |
| Encapsulado | — | 28-pin ceramic DIP (J) with quartz window |
| Estado del ciclo de vida | — | NRND (Not Recommended for New Designs) |