EP1810JI-35 vs EP1810JI-45 Comparación
Comparación detallada lado a lado de EP1810JI-35 por Intel y EP1810JI-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JI-35 | EP1810JI-45 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $18,60 | $9,75 |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | — |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Encapsulado | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40 °C to +85 °C |
| Tensión de alimentación | 5 V (typical classic EPLD) | 5 V (TTL compatible) |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Tipo de montaje | Through-Hole (J-lead) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | — |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Propagation Delay (tPD) | — | 50 ns |
| Configurable I/O Lines | — | 48 |
| Technology | — | CMOS EPROM |
| Package Code | — | QCCJ |
| Package Type | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| Programming Method | — | UV-erase (windowed) / OTP via JEDEC |