EP1810JI-45 vs EP1810GI-45 Comparación
Comparación detallada lado a lado de EP1810JI-45 por Altera y EP1810GI-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JI-45 | EP1810GI-45 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $56,40 |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | UV Erasable Programmable Logic Device (EPLD) |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | — |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| Technology | CMOS EPROM | CMOS |
| Package Code | QCCJ | — |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | Ceramic Pin Grid Array with UV window |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | — |
| Temperatura de funcionamiento | -40 °C to +85 °C | [DATA_NEEDED: operating temperature range] |
| Tensión de alimentación | 5 V (TTL compatible) | [DATA_NEEDED: VCC range] |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 24 |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Speed Grade | — | -45 |
| Recuento de pines | — | 68 |
| Tipo de montaje | — | Through-Hole |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Estado RoHS | — | Non-compliant (ceramic PGA) |
| Lead-Free | — | No |