EP1810JM-45 vs EP1810GI-45 Comparación
Comparación detallada lado a lado de EP1810JM-45 por Altera y EP1810GI-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JM-45 | EP1810GI-45 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $56,40 |
| Device Family | Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 24 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 45 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | CMOS |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | Ceramic Pin Grid Array with UV window |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| Recuento de pines | 68 | 68 |
| Temperatura de funcionamiento | -55 C to +125 C (military grade) | [DATA_NEEDED: operating temperature range] |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Tipo de montaje | Surface Mount (J-lead) | Through-Hole |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - legacy mil-spec part] | Non-compliant (ceramic PGA) |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 |
| Speed Grade | — | -45 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| Tensión de alimentación | — | [DATA_NEEDED: VCC range] |