EP1810LC-20T vs EP1810LC-25T Comparación
Comparación detallada lado a lado de EP1810LC-20T por Intel y EP1810LC-25T por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-20T | EP1810LC-25T |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $8,40 |
| Family | Altera Classic EPLD | Altera Classic EP1810 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 900 gates | Approx. 900 |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | 5 V nominal |
| Package Type | PLCC-68 (J-lead) | — |
| Tipo de montaje | Surface Mount (socket-compatible) | Surface Mount |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| Estado RoHS | Non-compliant (legacy 5V PLCC) | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Dedicated Inputs | — | 16 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Encapsulado | — | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Technology | — | CMOS, UV-erasable / OTP |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |