EP1810LC-25T vs EP1810JC-25 Comparación
Comparación detallada lado a lado de EP1810LC-25T por Intel y EP1810JC-25 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-25T | EP1810JC-25 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,40 | $6,80 |
| Family | Altera Classic EP1810 | Altera/Intel Classic EPLD (EP1810 series) |
| Device Type | EPLD (Erasable/OTP Complex PLD) | — |
| Macrocells | 48 (4 quadrants x 12 macrocells) | 48 |
| Usable Gates | Approx. 900 | — |
| Dedicated Inputs | 16 | 12 |
| Bidirectional I/O Pins | 48 | — |
| External Clocks | 4 | — |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | -40 °C to 85 °C (industrial, per distributor listings) |
| Encapsulado | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) | 28-pin ceramic DIP (J) with quartz window |
| Tipo de montaje | Surface Mount | Through-hole |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable (windowed ceramic DIP) |
| I/O Standard | TTL-compatible 5 V | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - confirm with manufacturer] | [DATA_NEEDED: RoHS compliance status] |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| Erasure Method | — | UV light (windowed package) |
| Estado del ciclo de vida | — | NRND (Not Recommended for New Designs) |