EP1810LC-25T vs EP1810LI-25 Comparación
Comparación detallada lado a lado de EP1810LC-25T por Intel y EP1810LI-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-25T | EP1810LI-25 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,40 | $9,95 |
| Family | Altera Classic EP1810 | Altera Classic EPLD |
| Device Type | EPLD (Erasable/OTP Complex PLD) | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP |
| Macrocells | 48 (4 quadrants x 12 macrocells) | 48 |
| Usable Gates | Approx. 900 | 900 |
| Dedicated Inputs | 16 | 12 |
| Bidirectional I/O Pins | 48 | — |
| External Clocks | 4 | — |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Supply Voltage (VCC) | 5 V nominal | 4.5 V to 5.5 V (nominal 5 V) |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | — |
| Encapsulado | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) | 68-pin PLCC (J68, J-Lead) |
| Tipo de montaje | Surface Mount | — |
| Technology | CMOS, UV-erasable / OTP | — |
| I/O Standard | TTL-compatible 5 V | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - confirm with manufacturer] | unknown |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic | — |
| Maximum Counter Frequency | — | 40 MHz |
| I/O Pins | — | 48 |
| Global Clock Inputs | — | 4 |
| Interconnect | — | Programmable global and local buses |
| JESD-30 Package Code | — | S-PQCC-J68 |
| Process Technology | — | CMOS |
| Operating Temperature (Industrial 'I' suffix) | — | -40 C to +85 C |
| Programming Mode | — | EPROM/UV-erasable (windowed) and OTP |
| Development Tool | — | Altera MAX+PLUS II |
| Lead-Free Status | — | unknown |