EP1810LC-45 vs EP1810LI-45 Comparación
Comparación detallada lado a lado de EP1810LC-45 por Rochester Electronics y EP1810LI-45 por Rochester Electronics. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 ObsoleteRochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ ActivoComparación de especificaciones
| Parámetro | EP1810LC-45 | EP1810LI-45 |
|---|---|---|
| Marca | Rochester Electronics | Rochester Electronics |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $49,90 | $64,10 |
| Family | Altera Classic EPLD | Altera Classic |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | 900 |
| Macro Cells | 48 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Logic Array Blocks | 4 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximum Operating Frequency | 22.2 MHz | — |
| Supply Voltage (Vcc) | 5 V (±5%) | — |
| Process Technology | 5 V CMOS EPROM | — |
| Encapsulado | 68-pin PLCC (J-lead) | 68-pin PLCC / PQCC68 (J-Lead) |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | — |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status of Rochester-sourced part] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 48 |
| Maximum User I/O | — | 64 inputs / 48 outputs |
| Pin-to-Pin Logic Delay (tPD) | — | 45 ns |
| Counter Frequency (fCNT) | — | up to 100 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Technology | — | CMOS, UV-erasable EPROM configuration |
| Tensión de alimentación | — | 5 V |
| Rango de temperatura de funcionamiento | — | -40 C to +85 C (Industrial, 'I' suffix) |
| Logic Blocks | — | 12 LABs of 4 macrocells each |
| Configuration Memory | — | Non-volatile UV-erasable EPROM |
| Programming Method | — | Altera programming hardware with MAX+PLUS II / legacy tools |
| Manufacturer | — | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) |