EP1810LI-25 vs EP1810LI-35 Comparación
Comparación detallada lado a lado de EP1810LI-25 por Altera y EP1810LI-35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LI-25 | EP1810LI-35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $78,05 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 48 | 48 |
| Usable Gates | 900 | — |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Maximum Counter Frequency | 40 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| I/O Pins | 48 | — |
| Dedicated Inputs | 12 | — |
| Global Clock Inputs | 4 | — |
| Interconnect | Programmable global and local buses | — |
| Encapsulado | 68-pin PLCC (J68, J-Lead) | 68-pin PLCC (J-Lead, plastic) |
| JESD-30 Package Code | S-PQCC-J68 | — |
| Process Technology | CMOS | — |
| Operating Temperature (Industrial 'I' suffix) | -40 C to +85 C | — |
| Programming Mode | EPROM/UV-erasable (windowed) and OTP | — |
| Development Tool | Altera MAX+PLUS II | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | unknown | — |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Technology | — | CMOS, UV-erasable EPROM configuration cell |
| Tensión de alimentación | — | 5 V (TTL-compatible I/O) |
| Temperatura de funcionamiento | — | -40 C to +85 C (industrial, 'I' suffix) |
| Tipo de montaje | — | Surface Mount (PLCC socket compatible) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |