EP1C6T144ITN vs EP1C6T144I8N Comparación
Comparación detallada lado a lado de EP1C6T144ITN por Altera y EP1C6T144I8N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1C6T144ITN | EP1C6T144I8N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,95 | $18,75 |
| Series | Cyclone | — |
| Family | Cyclone I | Cyclone I (original Cyclone) |
| Logic Elements (LE) | 5,980 | — |
| Embedded Memory (RAM bits) | 92,160 | — |
| M4K RAM Blocks | 20 | — |
| User I/Os | 98 | — |
| PLLs | 2 | 2 |
| Encapsulado | 144-LQFP (T144) | TQFP-144 (22x22 mm, 0.5 mm pitch) |
| Package Pin Count | 144 | — |
| Lead Pitch | 0.5 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount (Gull-Wing, JEDEC LQFP) |
| Core Voltage | 1.5 V | — |
| I/O Voltage | 3.3 V (LVTTL / LVCMOS / SSTL-2 / SSTL-3 / LVDS) | — |
| Operating Temperature Grade | Industrial (-40 °C to +100 °C TJ) | — |
| Speed Grade | I (lead-free / industrial) | 8 |
| Process Node | 0.13 µm SRAM | — |
| Configuration | JTAG (IEEE 1149.1) via Quartus II / Quartus Prime | — |
| Estado RoHS | Compliant (Pb-free, suffix 'N') | Compliant |
| Logic Elements (LEs) | — | 5,980 |
| Process Technology | — | 130 nm |
| Core Voltage (VCCINT) | — | 1.5 V (1.425 V to 1.575 V) |
| Maximum Internal Frequency | — | 275.03 MHz |
| Embedded RAM Bits | — | 92,160 bits |
| Embedded RAM Blocks | — | M4K (4 Kbit each) |
| User I/O Pins (max) | — | 98 |
| Rango de temperatura de funcionamiento | — | -40C to +100C (Industrial) |
| Configuration Method | — | Serial (EPCS) / JTAG |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |
| LVDS Support | — | Yes (dedicated LVDS pairs) |
| DSP Blocks | — | Embedded multiplier blocks (no dedicated DSP block per Cyclone I) |