EP1M120F484I6M vs EP1M120F484I5N Comparación
Comparación detallada lado a lado de EP1M120F484I6M por Altera y EP1M120F484I5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1M120F484I6M | EP1M120F484I5N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $325,00 | $180,00 |
| Family | Mercury (EP1M) | Mercury |
| Logic Elements | 120,000 | — |
| System Gates | 480,000 (typical) | — |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | 484-BBGA, FCBGA (FineLine BGA) |
| Package Code | BGA, 484 balls, Fine-pitch | — |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Temperature Grade | Industrial | Industrial (-40C to +100C) |
| Speed Grade | -6 (slowest Mercury timing bin) | 5 |
| Tensión de alimentación | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| Estado RoHS | Compliant (M revision) | Compliant |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Supply Voltage (Core) | — | 1.71 V to 1.89 V (1.8 V nominal) |
| User I/Os | — | 303 |
| Logic Family | — | CMOS |
| Logic Elements / Cells | — | [DATA_NEEDED: logic element count] |
| Total RAM Bits | — | 49152 |
| Number of Gates | — | 4800 |
| Number of I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Transceivers | — | Integrated CDR up to 1.25 Gbps |
| Package Dimensions | — | 23 x 23 mm |
| Recuento de pines | — | 484 |
| Pitch | — | 1.0 mm |
| Lead-Free / Pb-Free | — | Yes (N suffix) |
| Tipo de montaje | — | Surface Mount |