EP1M350F780C5 vs EP1M350F780C6N Comparación
Comparación detallada lado a lado de EP1M350F780C5 por Altera y EP1M350F780C6N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ Última compraComparación de especificaciones
| Parámetro | EP1M350F780C5 | EP1M350F780C6N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.303,00 | $219,40 |
| Device Family | Mercury | — |
| Logic Elements (approx.) | 350,000 | — |
| User I/O Pins | 486 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Embedded Transceivers | High-speed CDR channels up to 1.25 Gbps | — |
| Core Voltage | 1.71 V to 1.89 V | — |
| Speed Grade | C5 (commercial, fastest) | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (TJ) | 0 C to 85 C |
| Encapsulado | 780-ball FCBGA (29 mm x 29 mm, 1 mm pitch) | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Supply Voltage Range | 1.71 V ~ 1.89 V | — |
| Supplier Device Package | 780-FBGA (29x29) | — |
| Encapsulado / Carcasa | 780-BBGA, FCBGA | — |
| Series | Mercury | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | Non-compliant (per some distributor listings) | [DATA_NEEDED: rohs_status] |
| Estado del ciclo de vida | Not Recommended for New Designs (NRND) | — |
| Family | — | Mercury (EP1M350) |
| Device Type | — | Loadable Programmable Logic Device (PLD) / FPGA |
| Logic Family | — | CMOS, SRAM-based LUT |
| System Gates | — | 350,000 |
| Logic Cells / Elements | — | 14,400 |
| User I/Os | — | 486 |
| Integrated Transceivers | — | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | — | 1.8 V |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | S-PBGA-B780 |
| Configuration Interface | — | JTAG (IEEE 1149.1) / passive serial |
| Nivel MSL | — | [DATA_NEEDED: msl_level] |
| Lead-Free | — | [DATA_NEEDED: lead_free] |
| Architecture | — | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | — | 780 |