EP1M350F780C6N vs EP1M350F780I5 Comparación
Comparación detallada lado a lado de EP1M350F780C6N por Intel y EP1M350F780I5 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ Última compraAltera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndComparación de especificaciones
| Parámetro | EP1M350F780C6N | EP1M350F780I5 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $219,40 | $178,00 |
| Family | Mercury (EP1M350) | — |
| Device Type | Loadable Programmable Logic Device (PLD) / FPGA | — |
| Logic Family | CMOS, SRAM-based LUT | — |
| System Gates | 350,000 | — |
| Logic Cells / Elements | 14,400 | — |
| User I/Os | 486 | — |
| Integrated Transceivers | Yes, with CDR up to 1.25 Gbps | — |
| Core Supply Voltage | 1.8 V | — |
| Encapsulado | 780-ball FC-FBGA (FINE LINE BGA-780) | 780-ball FineLine BGA (F780) |
| Terminal Form | Ball | — |
| Package Code (JEDEC) | S-PBGA-B780 | — |
| Temperatura de funcionamiento | 0 C to 85 C | — |
| Configuration Interface | JTAG (IEEE 1149.1) / passive serial | — |
| Estado RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | [DATA_NEEDED: msl_level] | — |
| Lead-Free | [DATA_NEEDED: lead_free] | [DATA_NEEDED: lead-free status] |
| Architecture | Look-up table (LUT)-based, optimized for high-speed serial I/O | — |
| Total Package Pins / Balls | 780 | — |
| Device Family | — | Altera Mercury (EP1M) Enhanced Configuration Device |
| Función | — | FPGA configuration PROM with integrated controller |
| Storage Density Code | — | 350 (high-density) |
| Supported Configuration Schemes | — | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | — | Configuration controller + flash memory array |
| Programming Method | — | In-system programmable via Altera Quartus / JTAG |
| Temperature Grade (suffix "I") | — | Industrial |
| Speed Grade | — | 5 |
| Target FPGA Compatibility | — | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | — | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | — | Yes |