EP1M350F780C7N vs EP1M350F780I5 Comparación
Comparación detallada lado a lado de EP1M350F780C7N por Intel y EP1M350F780I5 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndComparación de especificaciones
| Parámetro | EP1M350F780C7N | EP1M350F780I5 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $168,00 | $178,00 |
| Family | Mercury (EP1M350) | — |
| Device Type | FPGA / Loadable PLD | — |
| Logic Cells | 14,400 | — |
| Gate Count | 350,000 | — |
| Core Supply Voltage | 1.8 V | — |
| User I/Os | 486 | — |
| Total Pins | 780 | — |
| Package Type | FC-FBGA / FINE LINE BGA-780 | — |
| Terminal Pitch | 1.0 mm | — |
| Speed Grade | C7 (-7 commercial) | 5 |
| Temperatura de funcionamiento | 0 C to 85 C (commercial) | — |
| Logic Family | CMOS | — |
| Transceivers | Up to 18 channels, 1.25 Gbps CDR | — |
| Architecture | LUT-based, register-rich | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | Altera Mercury (EP1M) Enhanced Configuration Device |
| Función | — | FPGA configuration PROM with integrated controller |
| Storage Density Code | — | 350 (high-density) |
| Supported Configuration Schemes | — | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | — | Configuration controller + flash memory array |
| Programming Method | — | In-system programmable via Altera Quartus / JTAG |
| Encapsulado | — | 780-ball FineLine BGA (F780) |
| Temperature Grade (suffix "I") | — | Industrial |
| Target FPGA Compatibility | — | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | — | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | — | Yes |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |