EP1S10F672C6 vs EP1S10F672C7N Comparación
Comparación detallada lado a lado de EP1S10F672C6 por Intel y EP1S10F672C7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S10F672C6 | EP1S10F672C7N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $72,00 | $171,00 |
| Series | Stratix® I | Stratix |
| Family | Stratix FPGA | — |
| Logic Elements (LE) | 10,570 | — |
| Logic Array Blocks (LABs) | 1057 | — |
| Total Memory Bits | 920,448 bits | — |
| Embedded Memory | TriMatrix (MRAM/M4K) | — |
| DSP Blocks | 6 | 6 |
| Number of I/Os | 345 | — |
| Number of PLLs | 12 (6 per device side) | — |
| Core Voltage | 1.5 V | 1.5 V |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Encapsulado | 672-ball FineLine BGA (FBGA) | — |
| Temperatura de funcionamiento | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Maximum Core Frequency | 420.17 MHz | — |
| Configuration Modes | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements / Cells | — | 10,570 |
| Number of LABs/CLBs | — | 1,057 |
| Total RAM Bits | — | 920,448 |
| Number of User I/Os | — | 345 |
| Number of Gates | — | [DATA_NEEDED: total gate count] |
| Package Type | — | 672-BBGA (FBGA) 35 x 35 mm, 1.27 mm pitch |
| Maximum Operating Frequency | — | 420.17 MHz |
| Configuration Method | — | SRAM, JTAG, passive/active serial/parallel |
| Nivel MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |