EP1S25F1020C6N vs EP1S25F1020I6 Comparación
Comparación detallada lado a lado de EP1S25F1020C6N por Altera y EP1S25F1020I6 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S25F1020C6N | EP1S25F1020I6 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $450,00 | $1.530,00 |
| Family | Stratix | Stratix |
| Logic Elements (LE) | 25,660 | — |
| Logic Cells | 25,660 | — |
| Embedded Memory (bits) | 1,944,576 | — |
| User I/O Pins | 706 | — |
| LABs (Logic Array Blocks) | 2,566 | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| Encapsulado | 1020-ball FC-FBGA (33 x 33 mm, 1.0 mm pitch) | 1020-ball FC-FBGA (33 x 33 mm, 1 mm pitch) |
| Maximum Internal Clock Frequency | 450.05 MHz | — |
| Temperatura de funcionamiento | 0C to +85C (Commercial) | -40 °C to +85 °C (industrial) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs compliance per lot] |
| Configuration Method | JTAG or EPC configuration device | — |
| Family Generation | Stratix (1st generation) | — |
| Series | — | Stratix I |
| Logic Elements (LEs) | — | 25,660 |
| Logic Array Blocks (LABs) | — | 2,566 |
| Embedded Memory (RAM bits) | — | 1,944,576 bits (≈ 1.85 Mbits) |
| Maximum User I/O | — | 706 |
| Maximum Operating Frequency | — | 450 MHz (per datasheet reference) |
| Core Supply Voltage | — | 1.5 V |
| Configuration | — | Passive serial, fast passive parallel, JTAG, enhanced configuration device |
| On-chip PLL | — | Yes |
| DSP Blocks | — | Yes (Stratix DSP blocks) |