EP1S30B956C6 vs EP1S60B956C6 Comparación
Comparación detallada lado a lado de EP1S30B956C6 por Altera y EP1S60B956C6 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S30B956C6 | EP1S60B956C6 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $78,00 | $339,20 |
| Family | Stratix | — |
| Logic Elements (LEs) | 32,470 | — |
| Logic Array Blocks (LABs) | 3,247 | — |
| Embedded Memory Bits | 3,317,184 (approximately 3.4 Mbit) | — |
| Maximum User I/O | 683 | — |
| Process Technology | 130 nm CMOS | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| Temperatura de funcionamiento | 0 C to 85 C (Commercial) | 0 C to +85 C (Commercial) |
| Speed Grade | C6 | — |
| Encapsulado | 956-ball FCBGA (BGA-956), 40 x 40 mm, 1.27 mm pitch | 956-BBGA, FCBGA (40 x 40 mm) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Maximum Internal Frequency | 450.05 MHz (per family datasheet) | — |
| DSP Blocks | Yes (Stratix DSP blocks) | — |
| PLLs | Up to 12 | — |
| Configuration Modes | Passive Serial (PS), Passive Parallel (PP), JTAG | — |
| Estado RoHS | Not confirmed - pre-RoHS part | [DATA_NEEDED: RoHS status] |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Lead-Free | Unknown | — |
| Series | — | Stratix (EP1S) |
| Logic Elements | — | 57,120 |
| Total RAM Bits | — | 5,215,104 |
| Number of LABs/CLBs | — | 5712 |
| Number of I/O | — | 683 |
| Supplier Device Package | — | 956-BGA (40x40) |
| Core Voltage - Supply | — | 1.425 V to 1.575 V |
| Voltage - Supply | — | 1.425 V to 1.575 V |
| Número de pines | — | 956 |
| Form of Terminal | — | Ball (BGA) |
| Package Code | — | BGA / FCBGA |