EP1S40B956C6N vs EP1S30B956C6 Comparación
Comparación detallada lado a lado de EP1S40B956C6N por Intel y EP1S30B956C6 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S40B956C6N | EP1S30B956C6 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.050,00 | $78,00 |
| Series | Stratix | — |
| Family | Altera Stratix (1st generation) | Stratix |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Logic Elements (LEs) | 41,250 | 32,470 |
| Logic Array Blocks (LABs) | 4,125 | 3,247 |
| Embedded Memory | 3,423,744 bits (~3.4 Mbit) | — |
| Maximum User I/O | 683 | 683 |
| Tensión de alimentación | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (Commercial) | 0 C to 85 C (Commercial) |
| Encapsulado | 956-ball FineLine BGA (FCBGA) | 956-ball FCBGA (BGA-956), 40 x 40 mm, 1.27 mm pitch |
| Package Dimensions | 40 mm x 40 mm | — |
| Ball Pitch | 1.27 mm | — |
| Speed Grade | C6 (commercial, mid-speed) | C6 |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Active Serial | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Not confirmed - pre-RoHS part |
| Embedded Memory Bits | — | 3,317,184 (approximately 3.4 Mbit) |
| Core Voltage (VCCINT) | — | 1.5 V |
| Maximum Internal Frequency | — | 450.05 MHz (per family datasheet) |
| DSP Blocks | — | Yes (Stratix DSP blocks) |
| PLLs | — | Up to 12 |
| Configuration Modes | — | Passive Serial (PS), Passive Parallel (PP), JTAG |
| Lead-Free | — | Unknown |