EP1SGX25CF672C6 vs EP1SGX25CF672I7N Comparación
Comparación detallada lado a lado de EP1SGX25CF672C6 por Intel y EP1SGX25CF672I7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP1SGX25CF672I7N - Stratix GX FPGA, 25,660 LEs, 672-FBGA | Intel
EP1SGX25CF672I7N ⚠ Última compraComparación de especificaciones
| Parámetro | EP1SGX25CF672C6 | EP1SGX25CF672I7N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $171,00 | $171,00 |
| Family | Stratix GX | Stratix GX |
| Logic Elements (LE) | 25660 | — |
| Configurable Logic Blocks (CLB / LAB) | 2852 LABs | — |
| User I/Os | 455 | — |
| Embedded Memory Bits | 1944576 | — |
| Transceiver Channels | 4 to 20 (SERDES up to 3.1875 Gbps) | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Temperatura de funcionamiento | 0 C to 85 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Encapsulado | 672-BBGA (FBGA-672), 27 x 27 mm, 1.0 mm pitch | 672-ball FC-FBGA, 1.0 mm pitch |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Lead Free | Yes | — |
| Estado RoHS | Compliant (lead-free per DigiKey listing) | [DATA_NEEDED: RoHS compliance status] |
| Design Tool | Quartus II | — |
| Series Prefix | EP1SGX (Stratix GX first generation) | — |
| Series | — | EP1SGX25 |
| Logic Elements | — | 25,660 |
| Configurable Logic Blocks (CLBs) | — | 2,566 |
| Package Code | — | BGA (SQUARE) |
| Recuento de pines | — | 672 |
| Terminal Form | — | BALL |
| Temperature Grade (marking) | — | MILITARY (I7N suffix) |
| Combinatorial CLB Delay | — | 9.48 ns |
| Internal Clock Frequency | — | Up to 4,385.97 MHz (datasheet figure) |
| Lead-Free | — | Yes |
| Nivel MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |