EP1SGX25FF1020C4 vs EP1SGX25FF1020C5L Comparación
Comparación detallada lado a lado de EP1SGX25FF1020C4 por Altera y EP1SGX25FF1020C5L por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1SGX25FF1020C4 | EP1SGX25FF1020C5L |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Unknown | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $105,00 |
| Product Type | Field-programmable gate array (FPGA) | — |
| Device Family | Stratix GX | — |
| Logic Cells | 25,660 cells | — |
| Listed Frequency | 5,000 MHz | — |
| Process Technology | 130 nm | 130 nm CMOS |
| Family Base MPN | EP1SGX25F | — |
| Package Code | FF1020 | — |
| Speed-Grade Suffix | C4 | — |
| Programmability | Field programmable | — |
| Device Category | Programmable logic integrated circuit | — |
| Configuration Memory Technology | [DATA_NEEDED: configuration memory technology] | — |
| Logic Elements | [DATA_NEEDED: logic elements] | 25,660 cells |
| Adaptive Logic Modules | [DATA_NEEDED: adaptive logic module count] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory capacity] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| User I/O Count | [DATA_NEEDED: user I/O count] | — |
| Tensión de alimentación | [DATA_NEEDED: supply voltage] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature] | [DATA_NEEDED: operating temperature range] |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Stratix GX |
| Package Type | — | FC-FBGA (Flip-Chip Fine-pitch Ball Grid Array) |
| Recuento de pines | — | 1020 balls |
| Core Voltage | — | 1.5 V |
| Speed Grade | — | C5 (slowest tier) |
| Maximum Transceiver Data Rate | — | 3.125 Gbps |
| Maximum Operating Frequency | — | 5000 MHz (internal reference) |
| Tipo de montaje | — | Surface Mount |
| Memory Architecture | — | TriMatrix (M512/M4K/M-RAM blocks) |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, HSTL, SSTL |
| Configuration Scheme | — | Active serial (EPCS), passive serial, JTAG |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |