EP20K1000CF33I8N vs EP20K1500CF33C8ES Comparación
Comparación detallada lado a lado de EP20K1000CF33I8N por Altera y EP20K1500CF33C8ES por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K1000CF33I8N | EP20K1500CF33C8ES |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $210,00 | $288,00 |
| Family | APEX 20KC | — |
| Logic Elements | 38,400 cells | 51,840 |
| System Gates | 1,000,000 (approx.) | 1,500,000 |
| Maximum Internal Clock Frequency | 301.21 MHz | — |
| Propagation Delay | 1.79 ns | — |
| Number of Logic Elements / Cells | 38,400 | — |
| Process Technology | 0.15 µm CMOS | — |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Number of I/O Pins | 700 user I/O | — |
| Número de pines | 1020 | — |
| Package Type | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) | — |
| Temperatura de funcionamiento | -40 °C to +85 °C (industrial) | [DATA_NEEDED: operating temperature range] |
| Embedded Memory | Dual-port RAM via ESB blocks | — |
| PLL Count | 4 | — |
| Configuration Interface | IEEE 1149.1 JTAG, EPC serial/parallel | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance for ES variant] |
| Speed Grade | I8 | -1 (C8) |
| Series | — | APEX 20K (APEX 20KE family) |
| Manufacturer | — | Intel (formerly Altera) |
| Maximum Gates (Equivalent) | — | 2,392,000 |
| Embedded System Block (ESB) Bits | — | 442,368 |
| CAM Bits | — | 216 Kbit |
| Number of PLLs | — | 4 |
| Number of Clocks | — | 8 clock pins |
| Maximum User I/O | — | 808 (1020-FBGA) |
| Encapsulado | — | 1020-FBGA (FCBGA), 33x33 mm |
| Voltage - Supply (Core) | — | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) |
| I/O Standard Support | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Interface | — | ByteBlaster / MasterBlaster / Altera USB-Blaster |
| Sample Tier | — | ES (engineering sample) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |