EP20K1000CF672C8ES vs EP20K1000CF672C8 Comparación
Comparación detallada lado a lado de EP20K1000CF672C8ES por Intel y EP20K1000CF672C8 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP20K1000CF672C8ES - 1M-gate APEX20KE FPGA, 672-BGA | Intel
EP20K1000CF672C8ES ⚠ Última compraComparación de especificaciones
| Parámetro | EP20K1000CF672C8ES | EP20K1000CF672C8 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $285,00 | $245,09 |
| Family | APEX 20K (APEX20KE) | — |
| Logic Elements | 38,400 | — |
| Typical Gates | 25,920 | — |
| Maximum System Gates | 1,000,000 | — |
| Embedded Memory (ESB) | 216 Kbits | — |
| User I/O Pins | 508 | — |
| Encapsulado | 672-ball FineLine BGA | 672-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch |
| Speed Grade | C8 | — |
| Temperatura de funcionamiento | Commercial (0C to +85C) | 0C to 85C (commercial) |
| Process Technology | 0.18 µm CMOS | 0.15 um all-layer copper CMOS |
| Core Voltage (VCCINT) | 2.5 V | 1.8 V (typical) |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS, LVPECL, GTL, SSTL-2/3 | — |
| PLLs | 4 (ClockLock/ClockBoost) | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | — |
| Nivel MSL | 3 (168 hours) | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Estado RoHS | Compliant | unknown (legacy part, verify on lot) |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Series | — | APEX 20KC |
| System Gates | — | 1,000,000 |
| Logic Elements / Cells | — | 38,400 |
| Embedded RAM | — | 327,680 bits |
| User I/Os | — | 488 (datasheet), 508 (per some distributor listings) |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Number of Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Number of PLLs | — | 4 |
| Maximum User I/O Pins | — | 488 |
| I/O Voltage (VCCIO) | — | Multi-voltage (LVTTL/LVCMOS/LVDS/SSTL/GTL+ compatible) |
| Propagation Delay (typical) | — | 1.6 ns |
| Configuration Mode | — | FPP / Passive Serial / JTAG |