EP20K100EBC652-2X vs EP20K200EBC652-3 Comparación
Comparación detallada lado a lado de EP20K100EBC652-2X por Altera y EP20K200EBC652-3 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K100EBC652-2X | EP20K200EBC652-3 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $85,00 | $210,00 |
| Family | APEX 20KE | APEX-20KE |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | — |
| Embedded System Blocks (ESBs) | 26 | Yes (dual-port RAM / ROM / CAM) |
| Maximum RAM Bits | 53,248 | — |
| Maximum User I/O Pins | 246 | 376 |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Encapsulado | 652-ball BGA (EBC652) | 652-ball FineLine BGA (top-side, 1.27 mm pitch) |
| Speed Grade | -2 (faster commercial) | -3 |
| Process Technology | 0.18 µm CMOS, SRAM-based | — |
| Temperatura de funcionamiento | 0C to +85C (commercial) | 0C to +85C (EBC - Enhanced Commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | — |
| Clock Resources | Up to 4 DLLs, multiple global clocks | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Not RoHS (non-lead-free variant) |
| Logic Elements (LEs) | — | 8,320 |
| Logic Array Blocks (LABs) | — | 832 |
| Total RAM Bits | — | 106,496 |
| PLLs | — | 4 |
| Configuration Mode | — | JTAG / PS / Passive-serial / Passive-parallel |
| Process Node | — | [DATA_NEEDED: process node] |
| Core Voltage | — | [DATA_NEEDED: core voltage] |
| Estado del ciclo de vida | — | Obsolete - last time-buy period closed |