EP20K100EFC144-1 vs EP20K100ETC144-1N Comparación
Comparación detallada lado a lado de EP20K100EFC144-1 por Intel y EP20K100ETC144-1N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K100EFC144-1 | EP20K100ETC144-1N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $61,75 | $55,80 |
| Device Family | APEX 20KE | — |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | 53248 |
| Embedded System Blocks (ESBs) | Yes (memory + dedicated logic) | — |
| User I/Os | 93 | 92 |
| Propagation Delay | 1.6 ns | — |
| PLLs | 4 | — |
| Package Type | 144-ball FBGA (13x13 mm, 1.0 mm pitch) | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (multiVolt I/O) | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (commercial) | 0 °C to +85 °C |
| Process Technology | 0.15-µm all-layer copper | 0.22 µm CMOS |
| Configuration Method | SRAM (volatile) - external boot PROM required | — |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Unknown [DATA_NEEDED: RoHS status] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Family | — | APEX-20KE |
| Logic Cells | — | 4160 |
| System Gates | — | 100000 |
| Encapsulado | — | 144-LQFP (TQFP) |
| Core Voltage | — | 1.8 V |
| Embedded Array Blocks (EABs) | — | Yes (32-bit x 2K RAM/ROM/FIFO) |
| Configuration Interface | — | JTAG (IEEE 1149.1) / IEEE 1532 ISC |
| Programming Software | — | MAX+PLUS II / Quartus II (legacy) |
| Device Series | — | APEX 20K 416 Macro 92 IOs |