EP20K100EFC144-1 vs EP20K100ETC144-2N Comparación
Comparación detallada lado a lado de EP20K100EFC144-1 por Intel y EP20K100ETC144-2N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K100EFC144-1 | EP20K100ETC144-2N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $61,75 | $22,00 |
| Device Family | APEX 20KE | — |
| Device Type | FPGA (Field Programmable Gate Array) | FPGA (Field Programmable Gate Array) |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | — |
| Embedded System Blocks (ESBs) | Yes (memory + dedicated logic) | — |
| User I/Os | 93 | — |
| Propagation Delay | 1.6 ns | 1.6 ns |
| PLLs | 4 | — |
| Package Type | 144-ball FBGA (13x13 mm, 1.0 mm pitch) | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (multiVolt I/O) | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (commercial) | — |
| Process Technology | 0.15-µm all-layer copper | 0.22 µm all-layer copper-metal |
| Configuration Method | SRAM (volatile) - external boot PROM required | — |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Family | — | APEX-20KE |
| Number of Logic Elements/Cells | — | 4160 |
| Number of LABs/CLBs | — | 416 |
| Total RAM Bits | — | 53248 |
| Number of Gates | — | 263000 (typical) |
| Number of User I/Os | — | 92 |
| Encapsulado | — | 144-LQFP (TQFP, 20x20 mm, 0.5 mm pitch) |
| Operating Supply Voltage (Core) | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Operating Frequency | — | 250 MHz |
| Rango de temperatura de funcionamiento | — | 0 C to 85 C (TJ) |
| ESBs (Embedded System Blocks) | — | 4 |
| Programming Interface | — | JTAG (IEEE 1149.1) / FastON |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |