EP20K100QC240-1 vs EP20K100QC240-3N Comparación
Comparación detallada lado a lado de EP20K100QC240-1 por Intel y EP20K100QC240-3N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K100QC240-1 | EP20K100QC240-3N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $98,00 | $0,00 |
| Family | APEX 20K | APEX-20K |
| Device Type | FPGA (Field-Programmable Gate Array) | FPGA |
| Logic Elements (LEs) | 4,160 | — |
| Typical Gates | 100,000 | — |
| Maximum User I/O | 189 | — |
| Embedded RAM Bits | 53,248 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | — |
| Maximum Internal Frequency | 250 MHz | — |
| Speed Grade | -1 | — |
| Encapsulado | 240-pin PQFP (QFP-240) | 240-BFQFP |
| Package Code | S-PQFP-G240 | — |
| Terminal Form | Gull Wing | — |
| Propagation Delay | 1.6 ns (per datasheet, typical) | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (Commercial) | 0 C to 85 C |
| Tipo de montaje | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Programming | In-system (SRAM-based) via Quartus / MAX+PLUS II | — |
| Gate Count | — | 100000 gates |
| Logic Cells | — | 4160 cells |
| User I/O | — | 189 I/O |
| Distributed Memory | — | 53248 bits |
| Macrocells | — | 416 macrocells |
| Tensión de alimentación | — | 2.375 V to 2.625 V |
| Nominal Supply | — | 2.5 V |
| Maximum Frequency | — | 167 MHz |
| Recuento de pines | — | 240 pins |
| Fabrication Process | — | 0.15 um all-layer copper-metal process |
| Package Pitch | — | 1.27 mm |
| Package Dimensions | — | 45 mm x 45 mm |
| Estado RoHS | — | unknown |
| AEC-Q100 | — | not_qualified |