EP20K200CB652C7ES vs EP20K200EBC652-3N Comparación
Comparación detallada lado a lado de EP20K200CB652C7ES por Altera y EP20K200EBC652-3N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K200CB652C7ES - APEX 20K 200K FPGA 652-BGA | Altera/Intel
EP20K200CB652C7ES ⚠ Última compraComparación de especificaciones
| Parámetro | EP20K200CB652C7ES | EP20K200EBC652-3N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $275,00 | $220,00 |
| Family | APEX 20K | — |
| Logic Elements | 8,320 | — |
| Embedded System Block (ESB) RAM | 106,496 bits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for 652-BGA] | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Speed Grade | -7 | -3 (slowest in APEX 20KE family) |
| Operating Temperature (Commercial) | 0 °C to +85 °C | — |
| Encapsulado | 652-BGA | 652-ball BGA |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Method | SRAM (volatile, requires external PROM on power-up) | — |
| PLL Count | Up to 8 | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS | — |
| JTAG (IEEE 1149.1) | Yes (boundary-scan) | — |
| Configuration Device Compatibility | EPC2, EPC8, EPC16, EPC64, microprocessor | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Nivel MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | APEX 20KE (APEX-20KE®) |
| Device Family | — | EP20K200 |
| System Gates | — | 200,000 |
| Logic Elements / Cells | — | 8,320 |
| Logic Array Blocks (LABs) | — | 832 |
| Macrocells | — | 832 |
| Embedded RAM | — | 106,496 bits |
| User I/Os (DigiKey listing) | — | 376 |
| User I/Os (digchip listing) | — | 277 |
| Propagation Delay | — | 2.33 ns |
| Internal Frequency (max) | — | 189 MHz |
| Process Technology | — | 0.22 µm CMOS |
| Core Supply Voltage | — | 1.71 V to 1.89 V (nominal 1.8 V) |
| I/O Supply (LVDS-capable) | — | LVDS, 2.5 V referenced (per source variant) |
| Operating Temperature (TJ) | — | 0 °C to 85 °C (commercial) |
| Configuration | — | JTAG (IEEE 1149.1), Passive Serial |