EP20K200CF484C7N vs EP20K200BC484-2X Comparación
Comparación detallada lado a lado de EP20K200CF484C7N por Altera y EP20K200BC484-2X por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K200CF484C7N - APEX-20K 200K Gates FPGA 484-FBGA | Intel/Altera
EP20K200CF484C7N ObsoleteComparación de especificaciones
| Parámetro | EP20K200CF484C7N | EP20K200BC484-2X |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $62,00 | $95,00 |
| Series | APEX-20K | EP20K200 |
| Logic Elements / Cells | 8,320 | — |
| Total RAM Bits | 106,496 | — |
| Number of Gates (typical) | 200,000 | — |
| Number of I/O | 382 | — |
| Voltage - Supply (VCCINT) | 1.71 V to 1.89 V | — |
| Encapsulado / Carcasa | 484-BBGA (FineLine BGA) | — |
| Supplier Device Package | 484-FBGA (23x23 mm) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +85C (commercial grade) | — |
| Number of PLLs | 4 | — |
| Embedded Array Blocks (EABs) | Configurable as RAM/ROM/FIFO | — |
| Programmable Logic Blocks | APEX LAB architecture | — |
| MultiVolt I/O Support | 1.8V / 2.5V / 3.3V / 5V | — |
| Configuration Method | SRAM-based, in-system reconfigurable | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (per supplier listings) |
| Estado del ciclo de vida | Obsolete (Altera/Intel APEX-20K family EOL) | — |
| Family | — | APEX-20K |
| Logic Elements | — | 8,320 |
| LABs/CLBs | — | 832 |
| Embedded RAM | — | 106,496 bits |
| User I/O Pins | — | 382 |
| Dedicated Inputs | — | 4 |
| Supply Voltage (VCCINT) | — | 2.375 V to 2.625 V |
| Temperatura de unión de funcionamiento | — | 0 °C to 85 °C |
| Encapsulado | — | 484-ball PBGA (BBGA-484) |
| Architecture | — | MultiCore™ (LUT + Embedded System Blocks) |
| Configuration | — | SRAM-based (requires external configuration memory) |
| Speed Grade | — | -2X |
| Maximum Clock Frequency (reference) | — | 178.57 MHz (per Altera datasheet for family) |