EP20K200CF484I9N vs EP20K200CF484C9N Comparación
Comparación detallada lado a lado de EP20K200CF484I9N por Altera y EP20K200CF484C9N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K200CF484I9N | EP20K200CF484C9N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $115,00 | $201,04 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 8,320 | — |
| Maximum Gates | 200,000 | — |
| Maximum Internal Frequency | 250 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Encapsulado | 484-pin FBGA (PBGA484), 1.0 mm pitch | 484-pin FineLine BGA (FBGA) |
| User I/O Count | 376 (368 user I/O + 4 dedicated inputs) | — |
| Speed Grade | I9 (industrial, highest-performance bin) | C9 (250 MHz) |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial temperature range -40C to +85C assumed for I-grade] | — |
| Programmable I/O Standards | LVTTL, LVCMOS, PCI | — |
| Configuration Interface | JTAG IEEE 1149.1, ByteBlaster/BitBlaster serial | — |
| On-chip Memory | Embedded System Blocks (ESBs) for distributed RAM/ROM | — |
| Lead-Free (Pb-free) | Yes (N suffix) | — |
| Estado RoHS | Compliant | Compliant |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Typical Gates | — | 200,000 |
| Logic Elements | — | 8,320 |
| Embedded System Block (ESB) Bits | — | 106,496 |
| Maximum User I/O | — | 376 |
| Frecuencia de reloj máxima | — | 250 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| Temperature Grade | — | Industrial (0C to +85C) |
| Tipo de montaje | — | Surface Mount (BGA) |
| Configuration Scheme | — | SRAM-based, supports passive serial/parallel and JTAG |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |