EP20K200RC208-2 vs EP20K200RC208-3 Comparación
Comparación detallada lado a lado de EP20K200RC208-2 por Altera y EP20K200RC208-3 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K200RC208-2 | EP20K200RC208-3 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $79,67 | $95,00 |
| Series | APEX-20K | APEX 20K |
| Family | APEX-20K MultiCore FPGA | APEX-20K® |
| Logic Elements (LEs) | 8320 | — |
| System Gates | 200,000 (typical) | — |
| Embedded Memory (bits) | 106,496 | 106,496 |
| Maximum User I/O | 144 | — |
| Encapsulado | 208-BQFP / 208-RQFP with Exposed Pad | 208-RQFP Exposed Pad (BFQFP) |
| Recuento de pines | 208 | — |
| Speed Grade | -2 (mid-speed, industrial) | -3 |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40°C to +85°C (Industrial) |
| Supply Voltage (Core) | [DATA_NEEDED: core VCC] | — |
| Supply Voltage (I/O) | 3.3 V (multi-standard I/O) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + Altera legacy scheme | — |
| Process Technology | [DATA_NEEDED: process node] | 0.22 µm CMOS |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements / Cells | — | 8,320 |
| Total System Gates | — | 200,000 |
| Number of I/O Pins | — | 144 |
| Core Voltage | — | 1.8 V |
| I/O Standard | — | LVDS (3.3 V / 2.5 V) |
| Maximum Operating Frequency | — | 167 MHz |
| PLLs | — | 4 |
| Programming Interface | — | IEEE 1149.1 JTAG |
| In-System Programmable | — | Yes |
| Hot Socketing | — | Yes |