EP20K300EFC672-1 vs EP20K300EBC652-1 Comparación
Comparación detallada lado a lado de EP20K300EFC672-1 por Altera y EP20K300EBC652-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K300EBC652-1 - APEX 20KE 300K Gates FPGA, 652-BGA | Altera
EP20K300EBC652-1 ⚠ Última compraComparación de especificaciones
| Parámetro | EP20K300EFC672-1 | EP20K300EBC652-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,40 | $215,00 |
| Family | APEX 20KE | APEX 20KE |
| Product Type | FPGA (Field-Programmable Gate Array) | — |
| System Gates | 300,000 | — |
| Logic Elements | 11,520 | — |
| Embedded RAM Bits | 147,456 | — |
| User I/O | 408 | — |
| Encapsulado | 672-ball FineLine BGA | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 1.8 V (1.71 V min, 1.89 V max) | — |
| Propagation Delay | 1.68 ns | — |
| Internal Frequency | 160 MHz (max performance grade up to 400 MHz) | — |
| Temperatura de funcionamiento | 0 C to 85 C (commercial) | 0C to +85C (industrial range varies) |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, GTL+, SSTL-2/3, LVDS | — |
| Architecture | MultiCore (LUT + ESB) | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Logic Family | CMOS, SRAM-based | — |
| Estado RoHS | unknown | unknown |
| Series | — | APEX-20KE® |
| Number of Logic Elements / Cells | — | 11520 |
| Total RAM Bits | — | 147456 |
| Number of Gates | — | 300000 |
| Number of I/O | — | 408 |
| Voltage - Supply | — | 1.71 V to 1.89 V |
| Encapsulado / Carcasa | — | 652-BGA (45x45 mm) |
| Supplier Device Package | — | 652-BGA |
| Core Operating Frequency (max) | — | [DATA_NEEDED: confirm from datasheet typical perf] |
| LVDS Support | — | Yes (per APEX 20KE family specification) |
| In-System Programmable | — | Yes (JTAG via ByteBlasterMV/MasterBlaster) |