EP20K30EFC144-2X vs EP20K60EFC144-2 Comparación
Comparación detallada lado a lado de EP20K30EFC144-2X por Altera y EP20K60EFC144-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K30EFC144-2X | EP20K60EFC144-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $58,50 | $12,75 |
| Device Family | Altera APEX 20K | — |
| Device Type | Loadable programmable logic device (FPGA/CPLD hybrid) | — |
| Typical Gates | 30,000 gates | 60,000 |
| Number of Logic Elements / Cells | 1,200 cells (third-party parametric listing) | — |
| Number of Macrocells | 192 | — |
| Number of User I/O | 93 | — |
| Number of Terminals | 144 | — |
| Terminal Form | Ball | — |
| Package Code | LBGA / 144-FBGA | — |
| Package Shape | Square | — |
| Core Supply Voltage | 1.8 V | 1.71 V to 1.89 V |
| Process Technology | 0.22 um | 0.18 µm CMOS |
| Speed Grade | -2X | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: exact operating temperature range] | — |
| Embedded RAM Bits | [DATA_NEEDED: embedded memory size] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration Schemes | [DATA_NEEDED: supported configuration schemes] | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Series | — | APEX-20K |
| Family | — | APEX-20KE (Enhanced, 1.8 V core) |
| Logic Elements | — | 2,560 |
| Total RAM Bits | — | 32,768 |
| User I/O | — | 92 to 93 |
| Internal Frequency (max) | — | 160 MHz |
| Propagation Delay | — | 1.72 ns |
| Encapsulado | — | 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) |
| Temperatura de funcionamiento | — | 0 °C to +85 °C (commercial) |
| JTAG Support | — | IEEE 1149.1 boundary scan |
| I/O Standards | — | LVTTL, LVCMOS, PCI, GTL+ |
| Configuration Method | — | Serial/Parallel passive, JTAG, EPC companion |