EP20K400CF672C8AA vs EP20K400CF672C7N Comparación
Comparación detallada lado a lado de EP20K400CF672C8AA por Intel y EP20K400CF672C7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400CF672C8AA | EP20K400CF672C7N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $145,00 | $160,00 |
| Family | APEX 20K | APEX 20KC |
| Number of Logic Elements/Cells | 16640 | — |
| Number of Logic Units (LEs) | [DATA_NEEDED: number of LUs] | — |
| Embedded System Blocks (ESBs) | 212 | — |
| On-chip RAM Bits | [DATA_NEEDED: total embedded memory bits] | — |
| Number of User I/O Pins | 488 | — |
| Package Type | 672-ball Fine-Pitch BGA (FBGA) | — |
| Number of Pins/Balls | 672 | — |
| Supply Voltage (Core) | 2.5 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, HSTL (multi-voltage I/O) | — |
| Propagation Delay | [DATA_NEEDED: typical propagation delay] | 2.5 ns (catalog) / 1.48 ns (some catalog) |
| Temperatura de funcionamiento | 0 C to 85 C (Commercial) | 0 C to 85 C (Commercial) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Packaging | Tray | — |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Configuration Interface | JTAG (IEEE 1149.1), passive serial, passive parallel asynchronous | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in provided data] |
| Maximum System Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Embedded Memory | — | 488 Kbits |
| Maximum User I/O | — | 488 |
| User I/O (per catalog) | — | 480 / 502 (per source) |
| Encapsulado | — | 672-ball FineLine BGA (FC-FBGA / BBGA) |
| Process Technology | — | 0.18-micron CMOS, all-layer copper interconnect |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 3.3 V / 2.5 V banked |
| Maximum Frequency | — | 375.94 MHz (internal) |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |
| Configuration Modes | — | PS, PPS, JTAG |