EP20K400FG672-2 vs EP20K400FI672-2X Comparación
Comparación detallada lado a lado de EP20K400FG672-2 por Altera y EP20K400FI672-2X por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400FG672-2 | EP20K400FI672-2X |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,00 | $171,00 |
| Family | APEX 20K | APEX 20K |
| Maximum System Gates | 1,060,000 (typ 400,000) | — |
| Logic Elements | 21,500 | 16,640 |
| Embedded System Blocks (ESBs) | 488 | — |
| Maximum RAM Bits | 212,992 | — |
| Macros / Logic Elements | 16,640 | — |
| Maximum User I/O | 488 | — |
| Speed Grade | -2 | -2X |
| Encapsulado | 672-ball FineLine BGA (FG672) | 672-ball BGA (FI672) |
| Core Voltage | 2.5 V (2.375 V to 2.625 V) | 1.8 V |
| Process Technology | 0.18 micron CMOS | 0.18 um CMOS, 6-metal |
| Temperatura de funcionamiento | 0C to +85C (commercial) | -40C to +85C (industrial) |
| Propagation Delay | 3.1 ns (typ) | — |
| Maximum Internal Clock Frequency | [DATA_NEEDED: maximum internal clock frequency] | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | non_compliant (legacy) | [DATA_NEEDED: RoHS compliance] |
| Toolchain Support | Quartus II / MAX+PLUS II only | — |
| Typical Gates | — | 400,000 system gates |
| Embedded Memory | — | 212,992 bits |
| User I/O Pins | — | 496 |
| Package Code | — | BGA |
| Terminal Form | — | Ball |
| No. of Terminals | — | 672 |
| Package Shape | — | Square |
| I/O Voltage Support | — | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) |
| Configuration Method | — | SRAM (serial EPROM or JTAG) |
| JTAG Support | — | Yes (IEEE 1149.1) |