EP20K400FI672-1 vs EP20K400FI672-1XN Comparación
Comparación detallada lado a lado de EP20K400FI672-1 por Intel y EP20K400FI672-1XN por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400FI672-1 | EP20K400FI672-1XN |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,00 | $171,00 |
| Series | APEX 20K | — |
| Device Family | APEX-20K Field Programmable Gate Array | — |
| Typical Gates | 400,000 | 400,000 |
| Logic Elements | 212,992 | 16,640 |
| Logic Array Blocks (LABs) | 16,640 | — |
| User I/O Pins | 502 | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 672 | — |
| Encapsulado | 672-ball PBGA (FineLine BGA, 1.0 mm pitch) | 672-ball FineLine BGA (FI672) |
| Package Code (JEDEC) | S-PBGA-B672 | — |
| Core Supply Voltage (VCCINT) | 2.5 V nominal (2.375 V to 2.625 V) | — |
| Process Technology | CMOS | 0.18 micrometer CMOS |
| Propagation Delay | 2.5 ns | — |
| Speed Grade | -1 | -1 |
| Temperatura de funcionamiento | Industrial (per 'I' suffix) | -40 C to +85 C (industrial) |
| Nivel MSL | 3 | 3 |
| Peak Reflow Temperature | 220 C | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Family | — | APEX 20K |
| Device | — | EP20K400 |
| Maximum User I/O Pins | — | 488 |
| Embedded System Memory | — | 212 Kbit |
| Number of PLLs | — | 4 |
| Core Supply Voltage | — | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | — | 2.5 V / 3.3 V |
| Package Size | — | 27 mm x 27 mm |
| Configuration Method | — | SRAM, JTAG, EPC serial PROM |
| JTAG Support | — | IEEE 1149.1 boundary-scan compliant |