EP20K400FI672-1XN vs EP20K400EFC672-1N Comparación
Comparación detallada lado a lado de EP20K400FI672-1XN por Intel y EP20K400EFC672-1N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400FI672-1XN | EP20K400EFC672-1N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $171,00 | $175,00 |
| Family | APEX 20K | APEX 20KE |
| Device | EP20K400 | — |
| Typical Gates | 400,000 | — |
| Logic Elements | 16,640 | — |
| Maximum User I/O Pins | 488 | — |
| Embedded System Memory | 212 Kbit | — |
| Number of PLLs | 4 | — |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | — |
| I/O Supply Voltage | 2.5 V / 3.3 V | — |
| Process Technology | 0.18 micrometer CMOS | 0.22 µm CMOS |
| Encapsulado | 672-ball FineLine BGA (FI672) | 672-ball FC-FBGA |
| Package Size | 27 mm x 27 mm | — |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | 0 °C to 85 °C (industrial) |
| Configuration Method | SRAM, JTAG, EPC serial PROM | — |
| JTAG Support | IEEE 1149.1 boundary-scan compliant | — |
| Speed Grade | -1 | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | 3 | — |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| User I/Os | — | 502 (488 per Mouser listing) |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V |
| Maximum Core Frequency | — | 368 MHz |
| Propagation Delay | — | 2.5 ns |
| Architecture | — | MultiCore (LUT + product-term + EAB) |
| PLLs | — | 4 |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| Tipo de montaje | — | Surface Mount |