EP20K400FI784-2 vs EP20K400FI784-1 Comparación
Comparación detallada lado a lado de EP20K400FI784-2 por Altera y EP20K400FI784-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400FI784-2 | EP20K400FI784-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $82,40 | $175,00 |
| Device Family | APEX 20K | — |
| Typical Gates | 400,000 | — |
| Logic Elements (LEs) | [DATA_NEEDED: logic elements count] | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Dedicated Inputs | 4 | 4 |
| Nominal Core Supply Voltage (VCCINT) | 2.5 V | — |
| VCCINT Range | 2.375 V to 2.625 V | — |
| Speed Grade | -2 | — |
| Rango de temperatura de funcionamiento | -40 °C to +100 °C | — |
| Package Type | S-PBGA-B784 (FineLine BGA) | 784-ball Fine-pitch BGA (S-PBGA-B784) |
| Package Pin Count | 784 balls | — |
| Ball Pitch | 1.000 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Device Form Factor | Loadable PLD | — |
| Process Technology | [DATA_NEEDED: process node] | 0.18 µm CMOS, 6-layer metal |
| Configuration Memory | SRAM-based (volatile) | — |
| Family | — | APEX 20K |
| Series | — | EP20K400 |
| Device Type | — | Loadable PLD (FPGA-class) |
| Usable Gates | — | 400,000 |
| Logic Elements | — | 1,560 |
| Embedded Memory (EAB RAM) | — | 212,992 bits |
| Maximum User I/O | — | 488 |
| Maximum Internal Clock Frequency | — | 6.1 GHz |
| Temperatura de unión de funcionamiento | — | -40°C to +100°C (industrial 'I') |
| Supply Voltage - Core | — | 1.8 V |
| I/O Standards Supported | — | 3.3 V / 5 V PCI, LVTTL, LVCMOS |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Lead-Free / RoHS | — | [DATA_NEEDED: RoHS status] |