EP20K400GC655-1 vs EP20K400BC652-1X Comparación
Comparación detallada lado a lado de EP20K400GC655-1 por Intel y EP20K400BC652-1X por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete
Comparación de especificaciones
| Parámetro | EP20K400GC655-1 | EP20K400BC652-1X |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $135,00 | $140,00 |
| Family | APEX 20K | APEX 20K |
| Series | EP20K400 | APEX 20KE |
| Logic Elements | 16,640 | — |
| Maximum Gates | 1,052,000 | — |
| Typical Gates | 400,000 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| Total RAM Bits | 212,992 | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 6 | 4 |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | — |
| Encapsulado | 655-pin CPGA (Ceramic Pin Grid Array) | 652-ball PBGA (45 x 45 mm, 1.27 mm pitch) |
| Recuento de pines | 655 | — |
| Tipo de montaje | Through-Hole | Surface Mount |
| Temperatura de funcionamiento | 0 °C to +85 °C (commercial) | Industrial (per datasheet) |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| Estado RoHS | Non-compliant (contains lead in ceramic package) | [DATA_NEEDED: RoHS status not stated in retrieved snippets] |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Embedded Memory (bits) | — | 212,992 |
| Embedded Array Blocks (EABs) | — | 104 x 2,048 bits |
| PLLs | — | 4 |
| DLLs | — | 4 |
| Maximum Frequency | — | 250 MHz |
| Propagation Delay (pin-to-pin) | — | 2.5 ns |
| Core Voltage | — | 2.5 V |
| I/O Standard Support | — | LVTTL, LVCMOS, PCI, SSTL-2/3, LVDS |
| Programming Interface | — | IEEE 1149.1 JTAG |