EP20K400GC655-3X vs EP20K400GI655-1X Comparación
Comparación detallada lado a lado de EP20K400GC655-3X por Altera y EP20K400GI655-1X por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X ObsoleteComparación de especificaciones
| Parámetro | EP20K400GC655-3X | EP20K400GI655-1X |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $65,00 | $160,00 |
| Series | APEX-20KC | — |
| Family | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) | APEX 20K |
| Manufacturer | Altera (now Intel FPGA) | — |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | — |
| Total RAM Bits | 212,992 bits | — |
| Maximum Internal Frequency | 167 MHz (speed grade -3) | — |
| Process Technology | 0.22 µm CMOS | CMOS, SRAM-based configuration |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V (LVDS support per APEX 20KE datasheet) | — |
| Encapsulado / Carcasa | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) | — |
| Tipo de montaje | Through-Hole (CPGA, ceramic) | Through-Hole (PGA) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) |
| Speed Grade | -3 (fastest) | -1 |
| Suffix Code | -X (extended / ceramic CPGA variant) | — |
| I/O Count | [DATA_NEEDED: max user I/O] | — |
| JTAG / Boundary Scan | IEEE 1149.1 (per APEX 20K family) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] | Compliant |
| Device | — | EP20K400 |
| Logic Elements | — | 16640 |
| Number of Terminals | — | 655 |
| User I/O Lines | — | 502 |
| Dedicated Inputs | — | 4 |
| Package Type | — | Ceramic Pin Grid Array (CPGA) |
| Package Code (JESD-30) | — | S-CPGA-P655 |
| Package Equivalence Code | — | SPGA655,47X47 |
| Package Body Material | — | CERAMIC (metal-sealed co-fired) |
| Propagation Delay | — | 2.5 ns (typical for -1 grade) |
| Nivel de sensibilidad a la humedad (MSL) | — | 1 |
| Peak Reflow Temperature | — | 220 C |