EP20K600CB652C9N vs EP20K600CB652C7N Comparación
Comparación detallada lado a lado de EP20K600CB652C9N por Intel y EP20K600CB652C7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K600CB652C9N | EP20K600CB652C7N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $128,00 | $305,00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD (FPGA) | SPLD / Loadable PLD (FPGA) |
| Typical Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 |
| Maximum User I/O | 488 | — |
| Encapsulado | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) | 652-ball BGA (PBGA-652, S-PBGA-B652) |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 um all-layer copper-metal |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Speed Grade | C9 (~1.48 ns propagation delay) | — |
| Architecture | MultiCore LUT + embedded system memory (ESB) | — |
| On-chip Memory | Embedded system memory blocks (dual-port RAM, FIFO) | — |
| Configuration Interface | JTAG (IEEE 1149.1) and serial/PROM configuration | — |
| Temperatura de funcionamiento | 0 C to 85 C (commercial) | 0 C to 85 C |
| Tipo de montaje | Surface Mount (BGA) | — |
| Pin/Pin Compatibility | Pin-compatible with APEX 20KE devices of same package | — |
| Toolchain | Altera/Intel Quartus II (legacy APEX support) | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| System Gates | — | 600,000 |
| Embedded Memory (bits) | — | 311,296 |
| Maximum User I/Os | — | 488 |
| Propagation Delay | — | 1.48 ns |
| Internal Operating Frequency | — | 375.94 MHz |
| Package Dimensions | — | 45 x 45 mm |
| Ball Pitch | — | 1.27 mm |