EP20K600CB652I8 vs EP2A70B652C7 Comparación
Comparación detallada lado a lado de EP20K600CB652I8 por Intel y EP2A70B652C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K600CB652I8 | EP2A70B652C7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,00 | $10,51 |
| Family | APEX 20KC | APEX II (Field-Programmable Gate Array) |
| Series | EP20K600 | APEX II |
| System Gates | 600,000 | — |
| Logic Elements / Cells | 24,320 | — |
| Maximum Operating Frequency | 301.21 MHz | — |
| Propagation Delay (tpd) | 1.78 ns (CMOS) | — |
| Process Technology | 0.15 µm CMOS | — |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Temperatura de funcionamiento | -40 °C to +85 °C (Industrial) | — |
| Encapsulado | 652-ball FineLine BGA (S-PBGA-B652) | — |
| Package Code | BGA, square | — |
| Ball Pitch | 1.27 mm | — |
| Package Body Size | 45 mm × 45 mm | — |
| User I/O Lines | 488 | — |
| Dedicated Clock Inputs | 4 | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements (LEs) | — | 67200 |
| Typical Gates | — | 1140000 |
| Maximum User I/Os | — | 336 |
| Package Type | — | BGA-652 (FineLine BGA) |
| Package Size | — | 27 mm x 27 mm (approximate) |
| Operating Temperature Grade | — | Commercial (C) |
| Speed Grade | — | 7 |
| Core Voltage | — | 1.8 V |
| I/O Bank Voltage (VCCIO) | — | 1.5V / 1.8V / 2.5V / 3.3V (bank-dependent) |
| Configuration Interface | — | JTAG, Passive Serial |
| Tipo de memoria | — | Embedded SRAM blocks (ESBs) |
| PLL / Clock Management | — | Yes, dedicated PLL blocks |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |