EP20K600CF672-1X vs EP20K600CF672-3X Comparación
Comparación detallada lado a lado de EP20K600CF672-1X por Intel y EP20K600CF672-3X por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP20K600CF672-3X - 600K Gate APEX 20KC FPGA, F672, -3X Speed | Intel / Altera
EP20K600CF672-3X ObsoleteComparación de especificaciones
| Parámetro | EP20K600CF672-1X | EP20K600CF672-3X |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $95,00 | $98,00 |
| Series | APEX 20KC | APEX 20KC |
| Device Family | APEX 20KC MultiCore FPGA | — |
| Maximum Typical Gates | 600,000 | — |
| Logic Elements | 31,104 (per Altera APEX 20KC datasheet family) | 24,480 |
| Embedded System Blocks (ESBs) | up to 256 | 312 |
| Embedded Memory (max bits) | [DATA_NEEDED: ESB RAM bits] | — |
| PLLs | 4 | 4 |
| Maximum User I/O | [DATA_NEEDED: max user I/O count] | — |
| Encapsulado | 672-ball BGA (CF672), 1.27 mm pitch | 672-pin FineLine BGA (F672) |
| Speed Grade | -1 (industrial speed grade, X = lead-free) | -3X (fastest) |
| Process Technology | 0.18 um SRAM CMOS | 0.18 um CMOS, SRAM-based |
| Configuration Method | SRAM, JTAG (IEEE 1149.1), EPC passive serial | SRAM, serial/parallel, EPC support |
| Tensión de alimentación | [DATA_NEEDED: VCCINT/VCCIO] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial temp range] | 0C to +85C (commercial) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Nivel MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Estado RoHS | Compliant (per Alibaba distributor listing: "RoHS Compliant") | [DATA_NEEDED: rohs status] |
| Family | — | APEX 20K (MultiCore) |
| Typical Gates | — | 600,000 |
| Maximum System Gates | — | 1,537,000 |
| Maximum RAM Bits | — | 311,296 |
| Maximum User I/O Pins | — | 508 |