EP20K60EFC324-2X vs EP20K60EFC324-2N Comparación
Comparación detallada lado a lado de EP20K60EFC324-2X por Intel y EP20K60EFC324-2N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K60EFC324-2X | EP20K60EFC324-2N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,50 | $52,73 |
| Family | APEX-20KE | APEX 20K |
| Number of Logic Elements (LEs) | 2,560 | — |
| Typical Gates | 60,000 | — |
| Total RAM Bits | 32,768 | 32,768 |
| Number of I/O Pins | 196 | — |
| Number of Embedded System Blocks (ESBs) | 16 | — |
| Number of PLLs | 4 | — |
| Core Voltage | 1.71 V to 1.89 V | — |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Package Type | 324-FBGA (Fine-pitch BGA) | — |
| Package Dimensions | 19 mm × 19 mm | — |
| Operating Temperature Grade | Industrial (per -2 speed suffix) | — |
| Configuration Mode | Passive Serial / Passive Parallel (Async & Sync) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Series | — | APEX-20KE |
| Number of Logic Elements/Cells | — | 2,560 |
| Total System Gates | — | 60,000 |
| Number of Logic Array Blocks (LABs/CLBs) | — | 2,560 |
| Number of I/O | — | 196 |
| Core Voltage Supply | — | 1.71 V to 1.89 V (1.8 V typ.) |
| Internal Frequency (max) | — | 200 MHz |
| Propagation Delay | — | 1.72 ns |
| Operating Temperature Range (TJ) | — | 0 °C to 85 °C (commercial) |
| Encapsulado / Carcasa | — | 324-BGA (FineLine BGA, 19x19 mm) |
| Supplier Device Package | — | 324-FBGA (19x19) |
| Tipo de montaje | — | Surface Mount |
| Process Technology | — | 0.22 µm CMOS |
| Architecture | — | MultiCore (LUT + ESB memory + product-term) |
| Configuration Method | — | Passive Serial / JTAG (IEEE 1149.1) |