EP2A15F672I8 vs EP2A15F672C9 Comparación
Comparación detallada lado a lado de EP2A15F672I8 por Altera y EP2A15F672C9 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A15F672I8 | EP2A15F672C9 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $680,00 | $175,00 |
| Family | APEX II | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 µm all-layer copper (up to 8 metal layers) |
| Metal Layers | Up to 8 | — |
| Typical Gates | 600 K | — |
| Logic Elements / Cells | 16,640 | — |
| User I/Os | 492 | — |
| Embedded Memory | 416 Kbits | ESB dual-port RAM / FIFO |
| Maximum Internal Frequency | 435 MHz | 379 MHz |
| Propagation Delay (typ.) | 1.94 ns | — |
| Core Supply Voltage | 1.5 V (1.425 V – 1.575 V) | 1.5 V |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| Temperatura de funcionamiento | -40 °C to +100 °C (TJ, industrial) | 0 °C to 85 °C (commercial) |
| Encapsulado | 672-FBGA, FCBGA, 27 x 27 mm, 1.0 mm pitch | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| Tipo de montaje | Surface Mount (BGA) | — |
| I/O Standards | LVTTL, LVCMOS, LVDS, MultiVolt I/O | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Logic Family | — | APEX II (CMOS) |
| Usable Gates | — | 600 K |
| Logic Elements | — | 16640 |
| Macrocells | — | 1664 |
| Maximum User I/Os | — | 492 |
| I/O Supply Voltage | — | 3.3 V |
| Propagation Delay | — | 1.94 ns |
| High-Speed I/O Support | — | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Configuration Interface | — | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | — | On-chip PLLs for clock synthesis and deskew |
| Compliance | — | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan |