EP2A25F672C7N vs EP2A15F672C7N Comparación
Comparación detallada lado a lado de EP2A25F672C7N por Altera y EP2A15F672C7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A25F672C7N | EP2A15F672C7N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $171,00 |
| Family | APEX II | APEX II |
| Logic Elements | 24,320 cells | — |
| System Gates | Approximately 900,000 | — |
| User I/Os | 492 | 492 |
| Propagation Delay (tPD) | 1.69 ns | — |
| Internal Operating Frequency | Up to 500 MHz | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | 0.15 µm all-layer copper CMOS |
| Logic Family | CMOS | — |
| Package Type | 672-ball FC-FBGA (FineLine BGA) | — |
| Package Body Size | 27 x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (commercial) | Commercial (0C to +85C) |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | — |
| Programmable Logic Type | Loadable PLD (in-system programmable) | — |
| Embedded Memory | Embedded System Blocks (ESB) configurable as dual-port RAM/ROM | — |
| PLLs | Up to 4 | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Logic Elements (Cells) | — | 16,640 |
| Embedded Memory Bits | — | 425,984 |
| Metal Layers | — | Up to 8 |
| Core Voltage | — | 1.5 V |
| Maximum Internal Frequency | — | 500 MHz |
| Speed Grade | — | -7 |
| Encapsulado | — | 672-ball FC-FBGA (FineLine BGA) |
| I/O Standards Supported | — | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL |
| LVDS Data Rate | — | Up to 1 Gbps (True-LVDS) |
| Configuration Methods | — | JTAG, Passive Serial |