EP2A40B724I-9 vs EP2A40B724C9 Comparación
Comparación detallada lado a lado de EP2A40B724I-9 por Altera y EP2A40B724C9 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A40B724I-9 | EP2A40B724C9 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $605,00 | $395,38 |
| Family | APEX II | — |
| Logic Elements | 40,000 (typical) | — |
| Logic Cells | 38400 | — |
| Embedded Memory Bits | 655360 | — |
| Maximum User I/O | 540 (per EP2A40B724 family) | — |
| Encapsulado | 724-ball FCBGA / FineLine BGA | — |
| Package Code | B724 | — |
| Temperature Grade | Industrial ('I' suffix) | — |
| Temperatura de unión de funcionamiento | -40 C to +100 C (industrial) | — |
| Speed Grade | -9 (per APEX II speed bin) | — |
| Peak Reflow Temperature | 220 C | — |
| Core Voltage | 1.5 V (typical APEX II) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL | — |
| Configuration Interface | JTAG, Passive Serial | — |
| PLL | On-chip (per APEX II architecture) | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | [DATA_NEEDED: msl level] | [DATA_NEEDED: MSL level] |
| Series | — | APEX II |
| Logic Elements (LE) | — | 38,400 |
| Embedded RAM Bits | — | 655,360 (approximately 655 Kbits / 80 Kbytes) |
| Number of User I/O | — | 540 |
| Tensión de alimentación de funcionamiento | — | 1.425 V to 1.575 V (core) |
| MultiVolt I/O Support | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| Encapsulado / Carcasa | — | 724-BBGA, FCBGA (Flip-Chip BGA) |
| Supplier Device Package | — | 724-BGA (35x35 mm) |
| Tipo de montaje | — | Surface Mount |
| Temperatura de funcionamiento | — | 0C to +85C |
| Shipping Medium | — | Tray |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Architecture | — | LUT-based with embedded memory blocks |
| Typical Core Power | — | [DATA_NEEDED: ICCDAT typical] |