EP2A40F672C9ES vs EP2A40F672C7 Comparación
Comparación detallada lado a lado de EP2A40F672C9ES por Altera y EP2A40F672C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A40F672C9ES | EP2A40F672C7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $195,00 |
| Family | APEX II | APEX II |
| Logic Elements | 38,400 | 38,400 |
| System Gates | 1,500,000 | 1,500,000 |
| Maximum User I/O | 492 | 492 |
| Operating Frequency (max) | 366 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS, all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V | 1.5 V |
| Encapsulado | 672-pin FC-FBGA | 672-ball FC-FBGA (FineLine BGA) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Speed Grade | -9 | — |
| Configuration Modes | PS, PPS, PPA, JTAG, FPP | — |
| Embedded Memory (ESB) | Yes (RAM/ROM/CAM) | — |
| I/O Standards | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| Estado RoHS | unknown | Compliant |
| Macro Cells | — | 2,560 |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Pin-to-Pin Delay | — | 1.55 ns (C7 speed grade) |
| Maximum Internal Frequency | — | 562 MHz |
| High-Speed Interface | — | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport |
| PLLs | — | 4 |
| Package Dimensions | — | 27 x 27 mm, 1.0 mm pitch |
| Operating Temperature Grade | — | Commercial (per 'C' suffix in speed grade) |
| Lead-Free | — | Yes |