EP2A70B724C7N vs EP2A70B724C7 Comparación
Comparación detallada lado a lado de EP2A70B724C7N por Altera y EP2A70B724C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A70B724C7N | EP2A70B724C7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Unknown |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $188,00 | $0,00 |
| Family | APEX II (EP2A70) | APEX II |
| Device Type | FPGA (Field Programmable Gate Array) | FPGA (Field Programmable Gate Array) |
| Technology | 0.15 µm CMOS | CMOS |
| System Gates | 3,000,000 | — |
| Logic Cells / Logic Elements | 67,200 | — |
| Maximum Internal Frequency | 420 MHz | — |
| Propagation Delay (typ.) | 2.17 ns | — |
| User I/O Pins | 536 | — |
| Macrocells (memory blocks reference) | 16 | — |
| Core Supply Voltage | 1.5 V nominal | — |
| I/O Supply Voltage | MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant) | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (Commercial) | [DATA_NEEDED: operating-temperature range] |
| Encapsulado | 724-pin FCBGA (Flip-Chip BGA) | 724-pin FCBGA, 724-BBGA, or PBGA724 |
| Ball Pitch | 1.27 mm | — |
| Seated Height | 3.5 mm | — |
| Tipo de montaje | Surface Mount | — |
| Configuration Method | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) | — |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| Embedded Memory | Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Gate Count | — | 3,000,000 gates |
| Logic Cells | — | 67,200 cells |
| I/O Count | — | 540 I/O |
| Configuration or Memory Capacity | — | [DATA_NEEDED: exact embedded-memory or configuration-memory capacity] |
| Tensión de alimentación | — | 1.5 V |
| Maximum Frequency | — | 420 MHz |
| Fabrication Process | — | 0.15 µm |
| Loadable PLD Timing | — | 2.17 ns |
| Package Body Size | — | 35 mm x 35 mm |
| Package Pitch | — | 1.27 mm |
| Interface Capabilities | — | True-LVDS, LVPECL, PCML, and HyperTransport |
| REACH Status | — | unknown |
| AEC-Q100 Status | — | unknown |
| Lead-Free Status | — | unknown |