EP2C50F672C6N vs EP2C50F672C7 Comparación
Comparación detallada lado a lado de EP2C50F672C6N por Intel y EP2C50F672C7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP2C50F672C6N - 50K LE Cyclone II FPGA, 672-BGA | Intel / Altera
EP2C50F672C6N ⚠ Última compraAltera
EP2C50F672C7 - Cyclone II FPGA, 50K LE, 672-FBGA | Intel / Altera
EP2C50F672C7 ⚠ Última compraComparación de especificaciones
| Parámetro | EP2C50F672C6N | EP2C50F672C7 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $119,00 | $184,59 |
| Series | Cyclone II | — |
| Number of Logic Elements (LE) | 50,528 | — |
| Number of Configurable Logic Blocks (CLB) | 3,158 | — |
| Total Embedded Memory | 594,432 bits (594 Kbits) | — |
| Number of M4K Memory Blocks | 129 | — |
| Embedded 18x18 Multipliers | 150 | 86 (150 per device family datasheet figure) |
| Number of PLLs | 4 | — |
| User I/Os | 450 | — |
| Operating Supply Voltage (Core) | 1.15 V to 1.25 V | — |
| Temperatura de funcionamiento | 0C to +85C (commercial junction, -C6 grade) | — |
| Speed Grade | -6 (mid-tier) | -7 |
| Encapsulado | 672-ball FineLine BGA (FBGA-672), 1.0 mm pitch | 672-ball FineLine BGA (FBGA-672) |
| Tipo de montaje | Surface Mount (SMD/SMT) | — |
| Process Technology | 90 nm CMOS, low-k dielectric | 90 nm CMOS with low-k dielectric |
| Lead-Free / RoHS | Yes (LEAD FREE per datasheet) | Lead-Free / RoHS compliant per Heisener listing |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG, Fast Passive Parallel (FPP) | Passive Serial (PS), Active Serial (AS), JTAG |
| Family | — | Cyclone II |
| Logic Elements (LE) | — | 50,528 |
| Embedded Memory Bits | — | 594,432 bits |
| Embedded Memory Blocks | — | 250 M4K blocks (4 Kbit each) |
| User I/O Pins | — | 450 |
| Phase-Locked Loops (PLL) | — | 4 |
| Global Clock Networks | — | 16 |
| Core Voltage (VCCINT) | — | 1.2 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V (per bank) |
| Temperature Grade | — | Commercial (0C to +85C junction) |